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7-2
External Memory Performance
SV51008
2014.01.10
External Memory Performance
Table 7-2: External Memory Interface Performance in Stratix V Devices
Interface
DDR3 SDRAM
DDR2 SDRAM
RLDRAM 3
RLDRAM II
QDR II+ SRAM
QDR II SRAM
Voltage (V)
1.5
1.35
1.8
1.2
1.8
1.5
1.8
1.5
1.8
1.5
Soft Controller (MHz)
933
933
400
800
533
533
550
550
350
350
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use Altera's
External Memory Interface Spec Estimator tool.
Memory Interface Pin Support in Stratix V Devices
In the Stratix V devices, the memory interface circuitry is available in every I/O bank that does not support
transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.
Stratix V devices also provide an independent DQS logic block for each CQn pin for complementary read-
data strobe and clock operations
The memory clock pins are generated with double data rate input/output (DDRIO) registers.
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides more information about which pins to use for memory clock pins and pin location requirements.
Guideline: Using DQ/DQS Pins
The following list provides guidelines on using the DQ/DQS pins:
?
?
?
?
The devices support DQ and DQS signals with DQ bus modes of x4, x8/x9, x16/x18, or x32/x36.
You can use the DQSn or CQn pins that are not used for clocking as DQ pins.
If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os.
Some pins have multiple functions such as RZQ or DQ. If you need extra RZQ pins, you can use the
DQ/DQNs pins in some of the x4 groups as RZQ pins instead.
Altera Corporation
External Memory Interfaces in Stratix V Devices
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